1. Field of the Invention
The present invention generally relates to a complementary metal oxide semiconductor (CMOS) device and a method of forming the same. More particularly, the present invention relates to a CMOS device comprising single diffusion break (SDB) structures having different stresses and a method of forming the same.
2. Description of the Prior Art
In advanced semiconductor technology, fin field effect transistors (Fin FET) have taken the place of traditional planar transistors and become the mainstream of development. Generally, at the beginning of forming fin FETs, trenches are formed in a semiconductor substrate by at least a patterning processes, such as a photolithograph-etching process (PEP) to transfer the layout pattern to the semiconductor substrate and a plurality of fin structures are defined in the semiconductor substrate by the trenches. The trenches are then filled with an insulating dielectric material to form an isolation structure between the fin structures. A fin recess process is performed to recess the insulating dielectric material to expose the top surface and the upper sidewall of the fin structures. Afterward, a gate process is performed to form the gate structures striding across the fin structures, wherein the overlapping regions of the fin structures and the gate structures are the channel regions of the fin FETs.
It is well-known in the art that stresses such as compressive stress and tensile stress may have influences on device performance. A certain type of stress is usually applied on the devices by forming, for example, strained silicon in the source/drain region, or forming stressor layers such as a spacer layer or a contact etching stop layer (CESL) comprising proper stress directly covering the gate structure. However, for a complementary metal oxide semiconductor (CMOS) device comprising devices having complementary conductivities, introducing a compressive stress may improve the performance of the P-type device, but may adversely decrease the performance of the N-type device. On the other hand, introducing a tensile stress may improve the performance of the N-type device, but may adversely decrease the performance of the P-type device.
In light of the above, there is still a need in the field to provide a novel CMOS device wherein different stresses may be introduced in different areas to respectively improve the performance of the devices according to their conductivities.